Get2Chip Unveils Architectural-Level Pipeline Synthesis Solution
In Use Today In World's Most Demanding Pipelined Designs
Get2Chip(TM) Inc., the system on chip (SOC) synthesis leader based
here, today expanded its product portfolio with breakthrough
technology that automates pipelining for process-aggressive clock
frequencies found in high-performance SOC designs.
Pipeline Master(TM) is an architectural-level synthesis solution
in use today for the design of next-generation microprocessor
integrated circuits (ICs) that are some of the most demanding
pipelined designs. It is ideal for signal processing, networking,
telecom, encryption, speech recognition and graphics design because it
relieves the manual guesswork, offering better quality of results and
higher productivity. The technology accurately and automatically
transforms the number of stages in the pipeline -- or datapath -- and
assigns operations or logic to each stage. Finally, it includes an
integrated design for test (DFT) capability, bringing this function
for the first time to the architectural level of design.
"Our synthesis team has cracked a seemingly impossible problem and
we're extremely proud of the accomplishment," asserts Bernd U. Braune,
Get2Chip's chairman, president and chief executive officer (CEO). "It
has created the world's first highly optimized automatic pipeline
synthesis solution." Introducing Pipeline Master from Get2Chip
Manually coding at the register transfer level (RTL) of design and
re-coding for each tradeoff to be analyzed is a time-consuming and
inefficient practice. Pipelines, or the datapath, are designers'
attempts to "brute force" calculations that are repeated over and
over. A circuit pipeline processes multiple sets of data in parallel
but staggered by one or more clocks.
Pipeline Master was designed to optimize and to then make
tradeoffs between power and area throughput at the architectural
design phase. The breakthrough comes from enabling the interaction
between a number of design dimensions -- performance, area, power,
test, verification and process rules. The result is highly optimized
and automatic pipeline synthesis.
It uses accurate calculations of timing using process-accurate
models by applying interwoven high-level synthesis and logic
synthesis. The correct transformation tradeoffs relieve the manual
guesswork, offering better quality of results and higher productivity.
This feature guarantees no timing surprises with first-pass timing
closure from the architectural level.
(Transformations are automatic explorations of different
structures, such as adding one more adder, adding one more memory port
or two memory ports, or decreasing the design latency by one clock
cycle, by two clock cycles.)
Pipeline Master includes complex pipe/memory system interaction
and supports abstract descriptions. It automates implementation
details and includes all design rule check (DRC) correct
transformations.
Finally, it offers an integrated DFT capability, bringing DFT to
the architectural level.
Pricing and Availability
Pipeline Master is shipping now and is sold as an add on to
VOLARE. It is priced at $25,000, U.S. list, for a one-year
subscription. It runs on Linux, Sun Solaris and Hewlett Packard UX
operating systems.
Contact Lauro Rizzatti, Get2Chip's director of product marketing,
for more details on Pipeline Master. He can be reached via email at
lauror@get2chip.com or at (408) 501-9553.
About Get2Chip
Get2Chip, Inc., is a leading supplier of software products that
enable the design of the world's most complex integrated circuits
(ICs), primarily found in the communications, wireless, computer, and
consumer product markets. It was launched in 2000 by semiconductor
veterans and chip design tool experts from Cadence Design Systems,
Inc. (NYSE: CDN - news), LSI Logic Corporation (NYSE: LSI - news), Mentor Graphics
Corporation (Nasdaq: MENT - news), Synopsys (Nasdaq: SNPS - news) and VLSI
Technology -- now part of Philips Semiconductors (NYSE: PHG, AEX:
PHI). Its breakthrough front-end tool suite, VOLARE(TM), provides
fully integrated, multi-level synthesis that offers the flexibility to
do chip design at the architectural, register transfer (RTL) or gate
level. Its TOPOMO(TM)product integrates and automates block
partitioning, block placement, global routing and synthesis into one
front-end IC design tool. Both run on Sun and Hewlett Packard, and PC
under Linux. Get2Chip is privately held and has development centers in
San Jose, Calif., and Munich, Germany. Corporate headquarters: 2107
North First Street, Suite 350, San Jose, Calif. 95131. Telephone:
(408) 501-9600. Facsimile: (408) 501-9610. Email: info@get2chip.com.
Web Site: http://www.get2chip.com.
Get2Chip, Pipeline Master, VOLARE and TOPOMO are trademarks of
Get2Chip. Get2Chip acknowledges trademarks or registered trademarks of
other organizations for their respective products and services.
Contact:
Nanette Collins
Public Relations for Get2Chip
(617) 437-1822
nanette@nvc.com
